This application claims the priority of Korean Patent Application No. 2003-33346, filed on May 26, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to a nonvolatile memory device and a method of fabricating same. More particularly, the present invention relates to a one-time programmable (OTP) memory device and a method of fabricating the OTP memory device.
2. Discussion of the Related Art
Nonvolatile memory devices are devices from which data is not erased even with discontinued power and which are used to selectively program data according to the needs of a user. OTP memory devices are used for programming data only one time without erasing or adding data. Demand for OTP memory devices has been increasing.
A cell area of an OTP memory device may have a layout as shown in FIG. 1. FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III′ of FIG. 1. The cell structure of a conventional OTP memory device and a method of fabricating same will be described with reference to FIGS. 1 through 3.
As shown in FIGS. 2 and 3, the cell of the OTP memory device includes a tunnel oxide layer 15, a floating gate 20, a dielectric layer 40, and a control gate 50 in a stacked structure. The tunnel oxide layer 15 is formed on a substrate 1 on which an isolation layer 5 is formed. A source region 60 and a drain region 65 are formed in the substrate 1 under and adjacent both sides of the control gate 50. In the OTP memory device having the above-described stacked structure, as electrons are induced by a strong electric field and move through the tunnel oxide layer 15 with a thickness of about 100 Å, a threshold voltage of the cell area varies. As a result, the OTP memory device can perform a programming function. The tunnel oxide layer 15 is used as a gate oxide layer of the OTP memory device. The label tunnel oxide layer 15 derives from the fact that the electrons move inside the tunnel oxide layer 15.
Such an OTP memory device may be used to assist with functions of various types of semiconductor products. For example, an OTP memory device may be embedded in a liquid crystal display driver integrated circuit (LDI) so as to write various kinds of information. The process required to embed a cell of an OTP memory device within the stack structure shown in FIGS. 1 through 3 in an existing integrated circuit (IC) is complicated. When using an OTP memory device having the stacked structure, the number of processes for completing the IC increases and the cost of fabricating the IC increases.
The OTP memory device may be integrated with metal-oxide-semiconductor (MOS) transistors into one circuit on a semiconductor substrate. In order to fabricate the semiconductor IC, a thick oxide layer, for example, a gate oxide layer of the MOS transistor, is first formed on the substrate 1. Next, using a photolithographic process, the entire thick oxide layer or a portion thereof is removed from an area where the OTP memory device is to be formed. Thereafter, the thin tunnel oxide layer 15 is formed in the area. Materials for forming the floating gate 20, the dielectric layer 40, and the control gate 50 are subsequently deposited and patterned. Next, ions are implanted into an active area 10 to form the source region 60 and the drain region 65.
During removal of the entire thick gate oxide layer or a portion thereof using the photolithographic process, and the formation of the thin tunnel oxide layer 15, the gate oxide layer may be exposed to chemicals during formation and removal of a photoresist. Thus, the reliability of the MOS transistor may deteriorate. In particular, gate oxide layers of the MOS transistors may have different thicknesses so that the MOS transistors are used as high and low voltage transistors.